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Assignment 2 Due on Wednesday 24th of April, 2013. Assignment 3 Due on Wednesday 1st of May, 2013. Complete the counter code + Testbench by 24th April. Install Xilinx ISE before 24th April. ----------------------------------------------------------------- Jobs at CASE, Islamabad http://www.case.edu.pk/JobsCASE.pdf -----------------------------------------------------------------
FPGA Based System Design Final Exam Content -----------------------------
ALL Lectures
Material covered from Advanced Digital Design with Verilog HDL
Chapter 5 5.0 - 5.11 (both inclusive) 5.14 - 5.16 (both inclusive)
Chapter 6 6.0 - 6.9 (both inclusive)
Chapter 7 7.0 - 7.3 (both inclusive)
COURSE DESCRIPTION Information will be available soon.
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