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UET Taxila
http://www.uettaxila.edu.pk
Course Management System - UET Taxila
Student Control Area
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Inside Digital Design Accompany Lab Manual Lab-1.pdf
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9/14/2010 3:21:15 PM
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Lab-1: Combinational Logic, Model Sim
Adder Design, Decoder, Multiplexers, Comparator
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Introduction to Modelsim and Verilog .rar
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9/24/2010 7:12:08 PM
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Lab 2
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Inside Digital Design Accompany Lab Manual Lab-1 & 3.pdf
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10/5/2010 10:48:37 AM
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Lab 3: Flip-flop (D, Toggle, JK), Counters, Shift Register, Linear Feed Back shift Registers, Stop Watch with Seven Segment
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Very Simple CPU Design.pdf
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10/13/2010 11:08:38 AM
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Lab # 04: Design of a Very Simple CPU
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Lab5 & 6.doc
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11/5/2010 4:24:14 PM
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Lab 5 & 6
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Lab 7 & 8.doc
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11/5/2010
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Labs
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