The aim of the course is to understand fundamental limitations and constraints for designing digital integrated circuits in deep submicron technologies such as 40 nm or 28 nm. Special emphasis is given over technology scaling trends in photolithography, deep-submicron non-ideal effects in CMOS, transistor modeling, interconnect, signal integrity, low-power and low-voltage digital circuit design, leakage management, impact of process and supply voltage variations on timing, robustness, and memory design.

There is no well-defined text book for this course. All the course topics are covered from international research papers.

• Technology scaling and future trends
  • Design challenges of technology scaling, high-k/metal gate transistors, strained silicon, FinFETs, tri-gate fully depleted CMOS transistors
• Transistor models
  • Ion-implanted MOSFETs, effect of high fields on MOSFET, engineering model for short channel devices, low-voltage low-current continuous transistor model in all regions,
• Delay and timing modeling for performance optimization
  • Delay modeling and static timing verification, high speed electrical signaling, within-die variations in timing
• Variability
  • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution, Monte Carlo modeling of threshold variation due to dopant fluctuations, MOSFET matching, power-constrained CMOS scaling limits
• SRAM design issues
  • Static-noise margin analysis, SRAM cell design for stability , Read Stability and Write-Ability Analysis of SRAM Cells, SRAM leakage suppression, Fluctuation limits & scaling opportunities for CMOS SRAM cells, Word-line & Bit-line Pulsing Schemes
• Sequential circuits and timing
  • Comparative analysis of master-slave latches and flip-flops, multiply adder, using pulse-register technique, Flow-through latch and edge-triggered flip-flop hybrid elements, Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
• Power-performance optimization
  • Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization, analysis of power and performance for pipelined microprocessors
• Low-power digital circuit design
  • Leakage power management (stack effect, power gating, power supply scaling, multiple Vth design, dynamic body bias)
• Timing and synchronization
  • Delay locked loop, phase locked loop