Course Management System - UET Taxila
Course Management System - UET Taxila FPGA Based Design-VLSI Design   

 

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LECTURE NOTES

File Name Post Date Display
FPGA - Lecture 1.ppt 2/27/2013 10:38:02 AM
Lecture 1
FPGA - Lecture 2-1.ppt 2/27/2013 10:38:25 AM
Lecture 2 part 1
FPGA - Lecture 2-2.ppt 2/27/2013 10:38:47 AM
Lecture 2 part 2
Lecture 3-5.pdf 3/25/2013 6:24:47 AM
Lecture 3, 4 and 5 Chapter 5 of Adv. Digital Design with the Verilog HDL
Lecture 6- FPGA.pdf 4/17/2013 6:30:32 PM
Lecture 6 - FPGA
FPGA - Lab 6.pdf 4/17/2013 6:37:38 PM
Lab 6 - Some Parts will be completed later on
FPGA - Lab 7.pdf 4/17/2013 6:41:39 PM
Read the lab for next week, 24th of April
Lecture 7.pdf 4/17/2013 7:19:24 PM
FSM with Verilog
FSM Examples.pdf 4/17/2013 7:19:51 PM
Lecture 8.pdf 5/17/2013 11:01:46 AM
Chapter 6 - Part I
Lecture 9.pdf 5/17/2013 11:03:33 AM
Chapter 6 - Part II
Lecture 10.pdf 5/17/2013 11:06:14 AM
Chapter 6 - Part III
Chapter 7.pdf 6/5/2013 8:26:33 PM
Chapter 7
FPGA Final Exam content.txt 6/6/2013 8:24:34 PM
FPGA based Design Final exam content
FPGA_Chakwal_2K9_sessional-17-06-2013.xlsx 6/17/2013 8:21:42 PM
Sessional Marks - Contact me at earliest for any queries
FPGA_Chakwal_2K9_sessional-17-06-2013.pdf 6/17/2013 8:25:59 PM
Sessional marks - Contact me at earliest for any queries.
 

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